RM0029 Datasheet, PDF (669/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
Configurable Enhanced Modular IO Subsystem (eMIOS200)
22.3
External signals description
Each channel has one external input and one external output signal. Depending on the chip
integration, the input and output signals can be connected to two separate pins, or to a
single bidirectional pin. See Chapter 3: Signal Description for details.
22.4
22.4.1
Note:
Memory map/register definition
Memory map
The overall address map organization is shown in Table 398.
Whenever an access to either an absent register, an absent channel or a reserved address
is performed, the eMIOS200 responds by asserting a Transfer Error signal from the slave
bus (or STAC bus).
Table 398. SPC564A74xx, SPC564A80xx eMIOS memory map
Offset from
EMIOS_BASE
(0xC3FA_0000)
Register
Global registers
0x0000
EMIOS_MCR—Module Configuration Register
0x0004
EMIOS_GFR—Global FLAG Register
0x0008
EMIOS_OUDR—Output Update Disable Register
0x000C
EMIOS_UCDIS—Channel Disable Register
0x000C–0x001F
Reserved
Channel 0 registers
0x0020
EMIOS_CADR[0]—Channel A Data Register
0x0024
EMIOS_CBDR[0]—Channel B Data Register
0x0028
EMIOS_CCNTR[0]—Channel Counter Register
0x002C
EMIOS_CCR[0]—Channel Control Register
0x0030
EMIOS_CSR[0]—Channel Status Register
0x0034
EMIOS_ALTA[0]⁽¹⁾—Alternate A Register
0x0038–0x003F
Reserved
Location
on page 22-
678
on page 22-
680
on page 22-
681
on page 22-
682
on page 22-
682
on page 22-
683
on page 22-
684
on page 22-
685
on page 22-
689
on page 22-
690
Doc ID 15177 Rev 8
669/1740