RM0029 Datasheet, PDF (1311/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
Deserial Serial Peripheral Interface (DSPI)
30.9.3
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the
DSPI_SR is set indicating an overflow condition. Depending on the state of the ROOE bit in
the DSPI_MCR, the data from the transfer that generated the overflow is either ignored or
shifted in to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift
register. If the ROOE bit is cleared, the incoming data is ignored.
Draining the RX FIFO
Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the DSPI POP
RX FIFO Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO
Counter by one. Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO
Counter remains unchanged. The data, read from the empty RX FIFO, is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the DSPI_SR is set.
The RFDF bit is cleared when the RX_FIFO is empty and the DMA controller indicates that
a read from DSPI_POPR is complete or by writing a ‘1’ to it.
Deserial serial interface (DSI) configuration
The DSI configuration supports pin count reduction by serializing Parallel Input signals or
register bits and shifting them out in a SPI-like protocol. The timing and transfer protocol is
described in Section 30.9.6, Transfer formats. The received serial frames are converted to a
parallel form (deserialized) and placed on the Parallel Output signals or in the DSPI_DDR.
The various features of the DSI configuration are set in the DSPI DSI Configuration Register
(DSPI_DSICR).
The DSI frames can be from 4 to 32 bits. With Multiple Transfer Operation (MTO) the DSPI
supports serial chaining of DSPI modules within a device to create DSI frames up to 64 bits,
consisting of concatenated bits from multiple DSPIs. The DSPI also supports parallel
chaining allowing several DSPIs and off-chip SPI devices to share the same Serial
Communications Clock (SCK) and Peripheral Chip Select (PCS) signals. See Section ,
Multiple transfer operation (MTO) for details on the serial and parallel chaining support.
DSI Master mode
In DSI master mode the DSPI initiates and controls the DSI transfers. The DSI master has
four different conditions that can initiate a transfer:
● Continuous
● Change in data
● Trigger signal
● Trigger signal combined with a change in data
The four transfer initiation conditions are described in Section , DSI transfer initiation
control. Transfer attributes are set during initialization. Field DSPI_DSICR[DSICTAS]
determines which of the DSPI_CTAR registers will control the transfer attributes.
Slave mode
In DSI slave mode the DSPI responds to transfers initiated by a SPI or DSI bus master. In
this mode the DSPI does not initiate DSI transfers. Certain transfer attributes such as clock
polarity and phase must be set for successful communication with a DSI master. The DSI
slave mode Transfer attributes are set in the DSPI_CTAR1.
If the CID bit in the DSPI_DSICR is set and the data in the DSPI_COMPR differs from the
selected source of the serialized data, the slave DSPI will assert the MTRIG signal. If the
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