RM0029 Datasheet, PDF (822/1740 Pages) STMicroelectronics – The primary objective of this document

Enhanced Time Processing Unit (eTPU2)
RM0029
ETPU_CISR – eTPU Channel Interrupt Status Register
Host interrupt status (see Section , Interrupts and data transfer requests) from all channels
are grouped in ETPU_CISR. Their bits are mirrored from the Channel Status/Control
registers (see Section 24.4.7, Channel configuration and control registers) and Host must
write 1 to clear a status bit.
Offset: eTPU_A: eTPU_Base + 0x200; eTPU_B: eTPU_Base + 0x204
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CIS3
1
CIS3
0
CIS2
9
CIS2 CIS2
87
CIS2
6
CIS2
5
CIS2
4
CIS2
3
CIS2
2
CIS2
1
CIS2
0
CIS1
9
CIS1 CIS1
87
CIS1
6
W
CIC3
1
CIC3
0
CIC2
9
CIC2 CIC2
87
CIC2 CIC2 CIC2
654
CIC2
3
CIC2
2
CIC2 CIC2 CIC1
109
CIC1 CIC1
87
CIC1
6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18 19 20 21 22 23 24
25 26 27 28 29 30 31
R
CIS1
5
CIS1
4
CIS1
3
CIS1 CIS1
21
CIS1
0
CIS9
CIS8
CIS7
CIS6
CIS5
CIS4
CIS3
CIS2 CIS1
CIS0
W
CIC1
5
CIC1
4
CIC1
3
CIC1 CIC1
21
CIC1
0
CIC9
CIC8
CIC7
CIC6
CIC5 CIC4 CIC3 CIC2 CIC1 CIC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 504. ETPU_CISR Register
Table 452. ETPU_CISR field description
Field
Description
0-31
CISx—Channel x Interrupt Status
1: indicates that channel x has a pending interrupt to the Host CPU.
0: indicates that channel x has no pending interrupt to the Host CPU.
CICx—Channel x Interrupt Clear
0-31 1: clear interrupt status bit.
0: keep interrupt status bit unaltered.
For details about interrupts see Section , Channel interrupt and data transfer requests.
ETPU_CDTRSR – eTPU Channel Data Transfer Request Status Register
Data Transfer request status (see Section , Interrupts and data transfer requests) from all
channels are grouped in ETPU_CDTRSR. Their bits are mirrored from the Channel
Status/Control registers (see Section , ETPU_CxSCR – eTPU Channel x Status Control
Register).
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