RM0029 Datasheet, PDF (326/1740 Pages) STMicroelectronics – The primary objective of this document

External Bus Interface (EBI)
RM0029
EBI Bus Monitor Control Register (EBI_BMCR)
The EBI Bus Monitor Control Register controls the timeout period of the bus monitor and
whether it is enabled or disabled.
EBI_BASE+0xC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BMT
BME ⁰
0
0
0
0
0
0
W
RESET: 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 88. EBI Bus Monitor Control Register (EBI_BMCR)
Table 97. EBI Bus Monitor Control Register (EBI_BMCR) Field Descriptions
Name
Description
BMT —Bus Monitor Timing
16-23
BMT
This field defines the timeout period, in 8 external bus clock resolution, for the Bus Monitor. See
Section , Bus Monitor for more details on bus monitor operation.
Timeout Period = (2 + (8 * BMT)) / external bus clock frequency.
BME —Bus Monitor Enable
24
BME
This bit controls whether the bus monitor is enabled for internal to external bus cycles. The BME bit
is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0).
1: Enable bus monitor (for external TA accesses only)
0: Disable bus monitor
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