SST79LF008 Datasheet, PDF (72/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Advance Information
5.3.2 Clock Selection Control and Clock Domains
The 8051 CPU and core peripherals clock (CCLK) are
derived from three different clock sources—the on-chip ring
oscillator (RCLK), the PLL clock (PCLK), and the external
clock source (ECLK). The 8051 can be programmed to
switch the clock source during normal code execution. The
8051 clock source can be selected through the Clock
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
Source Control Register (CLKSRCCON). In addition
peripheral modules Time0, Timer1, and PWM have their
own clock selection control registers described in Section
10.0. The 8051 core clock, as well as some peripheral
clocks, are stopped when 8051 enters either Idle mode or
Power Down mode. for PCON register description, see
Section 11.4.
ECLK
X'tal
LCLK
PD
PLLSTOP
ROSCEN
EN
1
PLL
PCLK
MCLK ₁
0
CCLK
ST
0 PD
Ring Oscillator
EN
CLKSEL_8051
POWERGOOD
XCLK
RCLK
XTALEN
PD
IDL
Crystal Oscillator clock
Peripheral clock
LPC clock
8051 core clock
8051 CPU clock
Boundry internal to chip
FIGURE 5-4: SST79LF008 Clock Selection
The SST79LF008 clock usage and clock domains are summarized in the Table 5-4.
1245 ClockSel.0
TABLE 5-4: Clock Domains for SST79LF008 Modules
MODULE
Clock Domain
Clock status in Idle mode Clock status in Power Down
8051
8051 CPU clock
stop
stop
Timer 0/1
8051 core clock
run
stop
Peripheral clock
run
stop
Timer 2
8051 core clock
run
stop
Hibernation timer Crystal Oscillator clock
run
run
WDT
Peripheral clock
run
run/stop depends on (WDTCSR[7])
Fan Tachometer
Peripheral clock
run
run/stop depends on
(FANTIMEBASE[7:6])
PWM
8051 core clock
run
stop
Crystal Oscillator clock
run
run
ADC
8051 core clock
run
stop
DAC
8051 core clock
run
stop
PWM LED
Crystal Oscillator clock
run
run
UART
8051 core clock
run
stop
SPI
8051 core clock
run
stop
SMBus
8051 core clock
run
stop
PS/2
8051 core clock
run
stop
GPIO
LPC Interface
8051 core clock
LPC clock
run
stop (retain I/O state)
X¹
X¹
1. LPC clock status is controlled by the external LPC Host, it is not affected by 8051 Idle or Power Down mode.
T5-4.1245
©2006 Silicon Storage Technology, Inc.
72
S71320-01-000
10/06