SST79LF008 Datasheet, PDF (58/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
Advance Information
TABLE 4-8: aLPC Memory Write Cycle Field Definitions
Clock
Cycle
Field
Name
Field
SST79LF008
Contents
aLAD Comments
0-3
START 0,1,1,1
IN¹
aLFRAME# must be active (low) for the part to respond. Only the last
four clocks of the start field (before aLFRAME# transitioning high)
should be recognized. The START field contents indicate aLPC Firm-
ware Memory Write cycle (value = 1110).
LSb MSb
Order of bit transfer for this field: LS Bit first
4-7
IDSEL
0,0,0,0
IN¹
ID selects SST79LF0008 device to respond. If the IDSEL field
(or 1,0,0,0)
matches the device ID, then that particular device will respond to the
whole bus cycle. Valid IDs = 0000 or 0001.
LSb MSb
Order of bit transfer for this field: LS Bit first
8-35
ADDR
28-bit
address
IN¹
These 28 clock cycles make up the 28-bit starting memory address
A₂₇-A₀.
Order of bit transfer for this field: MS Nibble first, LS Bit first:
A24,A25,A26,A27, A20,A21,A22,A23, A16,A17,A18,A19,
A12,A13,A14,A15, A8,A9,A10,A11, A4,A5,A6,A7, A0,A1,A2,A3
36-39
MSIZE S0,S1,S2,S3
IN¹
Device will execute multi-byte write for N bytes.
Valid field values S = 0, 1, 2, 4, 7, 12, 13, 14
For the respective N = 1, 2, 4, 16, 128, 4K, 64K, 1M bytes
LSb MSb
Order of bit transfer for this field: LS Bit first
40-(m-1)
DATA
m = 40+8*N+
# of wait cycles
D0, D1,
…,
D(8*N)
IN¹
Data field consists of 8*N clock periods, where N is defined by
MSIZE field. The host will insert wait cycles and pause the data
stream when aLFRAME# goes low until it returns high, signifying that
the chip is ready for more data.
LSb MSb
Order of bit transfer for this field: LS Nibble first, LS Bit first, thus
DATA is transmitted starting with the least significant bit of Byte 0,
sequentially to the most significant bit of byte (N-1).
(m)-(m+3)
TAR0
1,1,1,1
IN¹
In these 4 clock cycles, the aLPC host has driven the aLAD pin to ‘1’.
This is the first part of the bus turnaround.
(m+4)-(m+7) TAR1
1,1,1,1
(float)
Float
The aLPC host floats the bus, and SST79LF008 takes control of the
bus after these 4 cycles, completing bus turnaround.
(m+8)-(m+11) RSYNC 0,0,0,0
OUT²
During these 4 clock cycles, the SST79LF008 generates a ready-
sync (RSYNC) indicating that it has received data.
(m+12)-(m+15) TAR0
1,1,1,1
OUT²
In these 4 clock cycles, SST79LF0008 has driven the bus to ‘1’.
This is the first part of the bus turnaround.
(m+16)-(m+19) TAR1
1,1,1,1
(float)
Float then SST79LF008 floats the bus, and the aLPC host resumes control of
IN¹
the bus after these 4 cycles, completing bus turnaround.
1. SST79LF008 reads field contents on the falling edge of the present clock cycle
2. Field contents are valid on the falling edge of the present clock cycle, and on the rising edge of the next clock cycle.
T4-8.0 1320
©2006 Silicon Storage Technology, Inc.
58
S71320-01-000
10/06