SST79LF008 Datasheet, PDF (176/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Advance Information
Figure 13-7 illustrates interaction between 8051 firmware
and SMBus controller hardware in Slave Transmit mode:
Slave Transmit mode:
1. Write 10H to SMSR. This will preset SMBus con-
troller for Slave Receive mode.
2. The hardware detects the START bit, automati-
cally sets the BSY bit, and receives the data byte
from the bus.
Then the hardware compares the value of
SAR[7:1] with the data received in the SDSR[7:1]:
If it matches, proceed to Step 3 to complete the
address phase.
If not, detect STOP condition when generated by
the master. The STOP condition clears BSY bit in
the hardware and completes the transaction.
3. The hardware sends ACK and sets the interrupt
pending bit to keep SMBus on hold. If the value of
the R/W# bit from the master (=SDSR[0]) is ‘1’,
then SMSRn_MOD0 is set and SMBus controller
automatically switches to Slave Transmit mode.
For example, when the master requires data from
the slave.
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
4. Write data to be transmitted to the SDSR and
clear the interrupt pending bit in SMCR. This
causes the data in SDSR to be sent automatically
over SMBus by controller hardware.
5. The hardware completes transmission of eight
data bits, receives the ninth bit during ACK clock
period, and sets interrupt pending. This keeps
SMBus on hold and allows the software to pro-
cess the transfer results and check errors.
Note that in the case of successful transmission,
allowing that arbitration has not failed, the master
is expected to send back an ACK to the slave—
lowering the SDAn line during ACK clock—except
for the last byte of the transaction.
6. Determine whether the last data byte has trans-
mitted.
If no, ACK was received. Return to Step 4 to start
the next data byte transmit cycle.
If yes, NACK was received. Clear SMSRn_MOD0
bit in SMSR register and clear the interrupt pend-
ing bit in SMCR. This will release the bus so that
the master will be able to generate a STOP condi-
tion which clears BSY bit in hardware and com-
pletes the transaction.
©2006 Silicon Storage Technology, Inc.
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