SST79LF008 Datasheet, PDF (1/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller plus
8 Mbit LPC Firmware Flash
SST79LF008
FEATURES:
SST79LF008 Notebook System Controller with 8 Mbit LPC Firmware Flash
Advance Information
• 8 Mbit LPC Firmware Memory SuperFlash device
with integrated LPC Keyboard, System configu-
ration, and Power Management controller
• ACPI 2.0 Compliant
• Conforms to LPC Interface Specification v1.1
– Includes support for Multi-byte Firmware
Memory Read/Write Cycles
- Firmware Memory 1-, 2-, 4-, 16-, and
128-byte Read Cycles
- Firmware Memory 1-, 2-, and
4-byte Write Cycles
– 15.7 MB/sec data transfer rate @ 33MHz clock
for Multi-Byte Read
– One ID pin for LPC Firmware Memory Device
selection
• LPC Firmware Memory
– 8 Mbit Single Block of on-chip SuperFlash
memory with two Shared-ROM modes
- Mode 1: 7 Mbit (896 KByte) for system BIOS
and 1 Mbit (128 KByte) for 8051 firmware
- Mode 2: 7.5 Mbit (960 KByte) for system BIOS
and 0.5 Mbit (64 KByte) for 8051 firmware
– Uniform 4 KByte Sectors and 64 KByte Blocks
with Erase capability
– 19 Lockable Blocks: one 16 KByte Boot Block,
two 8 KByte Parameter Blocks, one 32 KByte
Parameter Block, fifteen 64 KByte Main Blocks
- Block Locking Registers for individual block
Read-Lock, Write-Lock, and Lock Down
protection
– Lockable bottom 4 KByte sector for 8051 boot
firmware
– Erase-Suspend allowing Read or Program of the
other blocks
– Two-Cycle Command Set
• Non-Volatile Registers (NVR)
– 64-bit SST Pre-Programmed Identifier
– 192-bit OTP User Unique Identifier with Write-
Lock protection
– 3 KByte OTP User NVR area (UNVR)
– 4 KByte Erasable NVR area (ENVR) with Write-/
Read-Lock protection
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Fast Erase/Program Operations
– Sector-Erase Time: 55 ms (typical)
– Block-Erase Time: 55 ms (typical)
– Word-Program Time: 15 µs (typical)
• aLPC mode for Rapid Factory Programming
– Alternate LPC bus (aLPC) for in-system and
factory programming
– Auto Address Increment (AAI)
– Multi-Byte Program
– Chip Rewrite Time: 12 seconds (typical)
• Embedded Enhanced 8051 MCU
– 3- or 6-clock (selectable) per-instruction cycle
– Up to 33 MHz 8051 operating frequency
– Up to 128 KByte Program Address Space
– 256 Byte standard 8051 RAM
– 2 KByte on-chip expanded
Data RAM / Executable RAM (Scratch ROM)
– Extended up to 2 KByte Stack Space
– Four Levels of Interrupt Priorities and
Twelve Interrupt Vectors
– Power-saving IDLE and Power-Down modes
– Multiple Maskable Hardware Wake-up Events
(sources include: Hibernation timer, LPC, serial
interfaces, all GPIOs, and others)
• LPC Host Interfaces
– One 8042-style legacy KBC interface channel
– Two ACPI EC interface channels
– 32 8-bit LPC Host-to-8051 Mailbox Registers
– Programmable Base addresses for all channels
• System Interrupts
– IRQ1 and IRQ12 via serialized IRQ Interface
– Two EC SCI event outputs
– SMI via Serialized IRQ2 or SMI event output
• Hardware GA20 and CPU Reset Outputs Control
• 16 x 8 (24 pins) Key Scan Matrix expandable to
16 x 14 (30 pins)
• Three Independent PS/2 Ports
– Hardware driven receive and transmit protocols
– Integrated time-out control
• Two SMBus controllers/Three SMBus channels
– SMBus 2.0 compliant
– Master and Slave operation
– Internal multiplexer for SMBus channel selection
• Full-Duplex Enhanced UART channel
• SPI Master/Slave channel
©2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.