SST79LF008 Datasheet, PDF (196/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
Advance Information
16.2.5 ADC Data Register Lower Bits (ADDRL)
Location
7
6
5
4
3
2
1
0
Read
DD1
DD0
CD1
CD0
BD1
BD0
AD1
AD0
7F92H
Write
-
-
-
-
-
-
-
-
Reset
0
0
0
0
0
0
0
0
Symbol
-
DD[1:0]
CD[1:0]
BD[1:0]
AD[1:0]
Function
Not implemented
The least significant 2 bits of A/D conversion result for channel ACH3 or ACH7 (the
most significant 8 bits of A/D conversion result are stored in register ADDRD)
The least significant 2 bits of A/D conversion result for channel ACH2 or ACH6 (the
most significant 8 bits of A/D conversion result are stored in register ADDRC)
The least significant 2 bits of A/D conversion result for channel ACH1 or ACH5 (the
most significant 8 bits of A/D conversion result are stored in register ADDRB)
The least significant 2 bits of A/D conversion result for channel ACH0 or ACH4 (the
most significant 8 bits of A/D conversion result are stored in register ADDRA)
16.2.6 ADC Control and Status Register (ADCSR)
Location
7F93H
Read
Write
Reset
7
ADF
0
6
ADCEN
0
5
ADST
0
4
SCAN
0
3
CKS
0
2
CH2
0
1
CH1
0
0
CH0
0
Symbol
ADF
ADCEN
ADST
SCAN
CKS
CH[2:0]
Function
A/D conversion completion flag
Set by hardware in single mode when A/D conversion for the selected channel is
completed. Set by hardware in continuous mode when A/D conversion cycle for all
selected channels is completed. After ADF is set, the software must read ADCSR
register first, then write 0 to ADF in order to clear this bit. Writing 1 to ADF bit will be
ignored.
Enable ADC bit
1: Enable ADC
0: Disable ADC, and switch ADC into standby mode
If this bit is set, ADC enters/exits standby mode automatically when 8051 enters/
exits Power Down mode.
A/D conversion Start bit
1: ADC conversion is started (in progress)
0: ADC conversion is stopped
This bit can be set or cleared by software in either single or continuous mode. It is
cleared by hardware when conversion is completed in single mode only. The
ADST bit is also automatically cleared when ADCEN bit is cleared.
A/D conversion mode selection bit
1: Continuous mode
0: Single mode
A/D clock selection bit (A/D conversion time = 5 periods of ADC clock)
1: The frequency of ADC clock is FCCLK/12, FCCLK – 8051 core clock frequency
0: The frequency of ADC clock is FCCLK /24, FCCLK – 8051 core clock frequency
Note: ADC clock frequency must not exceed 2.0 MHz
Analog input channels selection bits
©2006 Silicon Storage Technology, Inc.
196
S71320-01-000
10/06