SST79LF008 Datasheet, PDF (172/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Advance Information
Set SMSR - Write D0H to SMSR
(This is done by software)
a) Write Slave Address to SDSR
b) Set BSY bit in SMSR (=F0H)
(This is done by software)
Generate START Condition
(This is done by hardware)
Send SDSR data byte,
Receive ACK bit.
Set INT bit in SMCR
(This is done by hardware)
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
More Data to
NO
Transmit?
(Done by software)
YES
Write New Data to Transmit to SDSR
(This done by software)
a) Clear BSY bit in SMSR (=D0H)
b) Clear INT bit in SMCR
(This is done by software)
Generate STOP Condition
(This done by hardware)
Clear INT bit in SMCR
(This done by software)
END
1245 SMBus_Master_XmitMode.0
FIGURE 13-5: SMBus Master Transmit Mode Operation
Figure 13-5 illustrates interaction between 8051 firmware
and SMBus controller hardware in Master Transmit mode:
Master Transmit Mode
1. Write D0H to SMSR. This presets the SMBus con-
troller for Master Transmit mode.
2. Write a 7-bit slave address to SDSR[7-1], and ‘0’
to SDSR[0] (R/W# bit). The R/W# bit determines
the direction of the transfer—if R/W# = 0 then the
master will send data to the slave. Set the BSY bit
in SMSR register. SMBus controller will generate
a START condition and automatically send SDSR
data over the SMBus.
3. The hardware completes transmission of eight
data bits, receives the ninth bit during ACK clock
period, and sets interrupt pending—keeping
SMBus on hold and allowing the software to pro-
cess the transfer results and check errors.
Note that in the case of successful transmission,
allowing that arbitration has not failed, the slave is
expected to send back an ACK to the master—
lowering the SDAn line during ACK clock.
4. Check for more data to transfer.
If the master has more data to transfer, the soft-
ware will write the next data byte to SDSR and
clear the interrupt pending bit in SMCR. This
causes the data in SDSR to be sent automatically
over the SMBus by controller hardware and
returns to Step 3.
If the master has no data to transfer, the software
will clear the BSY bit in SMSR and clear the inter-
rupt pending bit in SMCR. The controller hardware
will generate a STOP condition and release the
SMBus lines which completes the transaction.
©2006 Silicon Storage Technology, Inc.
172
S71320-01-000
10/06