SST79LF008 Datasheet, PDF (213/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
20.0 ACPI EMBEDDED CONTROLLER INTERFACE
Advance Information
20.1 ACPI Embedded Controller Interface Overview
ACPI specification defines a hardware and software inter-
face between the operating system and an embedded con-
troller (EC). This interface can be used by the standard
operating system driver to directly communicate with the
embedded controller. SST79LF008 provides two2 ACPI
compliant EC interfaces ECI0 and ECI1.
EC interface includes the following 8-bit registers: EC data
write register, EC data read register, EC command write
register, and EC status register. The host processor
accesses EC interface registers at two addresses in the
LPC I/O space. The 8051 core accesses EC interface reg-
isters at two addresses in the external data memory space.
Figure 20-1 describes the register mapping to the host I/O
space and 8051 memory space as well as access type for
each register.
TABLE 20-1: Embedded Controller Interface Mapping
LPC Host I/O Address and
Access Type
Address¹
Access
62H for ECI0
Write
68H for ECI1
Read
Function
Host-to-EC data write
Host-from-EC data read
66H for ECI0
Write
Host-to-EC command write
6CH for ECI1
Read
Host-from-EC status read
8051 Memory mapped Address and Access Type
Access
Address (MMCR register)
Read
7F53H (ECIDATA) for ECI0
Write
7F80H (ECIDATA1) for ECI1
Read
7F53H (ECIDATA) for ECI0
Write/Read
7F80H (ECIDATA1) for ECI1
7F54H (ECISTS) for ECI0
7F81H (ECISTS1) for ECI1
T20-1.1245
1. The default base address for EC host interface ports can be changed via SST79LF008 configuration registers (see Section 23.0).
For simplicity the description in Section 20.1 refers to default addresses.
When the Host writes command byte to EC through port
66H (6CH), the ECISTSn_C/D bit is set and the
ECISTSn_IBF bit is set in the respective EC status register.
When the Host writes data byte to EC through port 62H
(68H), the ECISTSn_C/D bit is cleared and the
ECISTSn_IBF bit is set in the respective EC status register.
When the Host reads data from EC through port 62H
(68H), the ECISTSn_OBF bit in the respective EC status
register is cleared. See detailed bit description for EC sta-
tus registers in Section 20.2.
©2006 Silicon Storage Technology, Inc.
213
S71320-01-000
10/06