SST79LF008 Datasheet, PDF (183/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
14.4 PS/2 MMCRs
There are five MMC registers associated with each PS/2
channel: PS/2 transmit register, PS/2 receive register, PS/2
control register, PS/2 status, and PS/2 alternate status reg-
isters. The transmit and receive registers are located at the
same address. There are also two registers common for all
channels: PS/2 time-out control register and PS/2 status 2
register.
14.4.1 PS/2 Transmit Registers
PS/2 transmit registers are write-only registers. To transmit
a data byte over the PS/2 interface by the PS/2 hard-
ware, it must be written while the PS2CRn_PS2_EN,
n=0-2,and PS2CRn_PS2_T/R, n=0-2 bits in the PS/2
Advance Information
control register and the PS2STSn_XMIT_IDLE bit in
the PS2 status register, or Alternate PS2 status regis-
ter are set. If any one of the three bits, are cleared,
PS2CRn_PS2_EN, PS2_T/R, or PS2STSn_XMIT_IDLE,
then the data written to the transmit register is ignored.
When PS/2 transmission is initiated, the PS2STSn_XMIT_
IDLE, n=0-2, and APS2STSn_XMIT_IDLE, n=0-2, bits are
automatically cleared. After successful completion of the
transmission, the PS2STSn_XMIT_IDLE and APS2STSn_
XMIT_IDLE bits are set, and the PS2CRn_PS2_T/R bit is
cleared in hardware. This automatically switches the
respective PS/2 channel into the receive mode.
14.4.1.1 PS/2 Transmit Register 0 (PS2TX0)
Location
7F41H
Write
Reset
7
PS2TX0
_7
0
6
PS2TX0
_6
0
5
PS2TX0
_5
0
4
PS2TX0
_4
0
3
PS2TX0
_3
0
2
PS2TX0
_2
0
1
PS2TX0
_1
0
0
PS2TX0
_0
0
14.4.1.2 PS/2 Transmit Register 1 (PS2TX1)
Location
7F45H
Write
Reset
7
PS2TX1
_7
0
6
PS2TX1
_6
0
5
PS2TX1
_5
0
4
PS2TX1
_4
0
3
PS2TX1
_3
0
2
PS2TX1
_2
0
1
PS2TX1
_1
0
0
PS2TX1
_0
0
14.4.1.3 PS/2 Transmit Register 2 (PS2TX2)
Location
7F49H
Write
Reset
7
PS2TX2
_7
0
6
PS2TX2
_6
0
5
PS2TX2
_5
0
4
PS2TX2
_4
0
3
PS2TX2
_3
0
2
PS2TX2
_2
0
Symbol
PS2TXn[7:0]
Function
PS/2 transmit, write only, register bits (n = 0-2)
1
PS2TX2
_1
0
0
PS2TX2
_0
0
14.4.2 PS/2 Receive Registers
PS/2 receive registers are read-only registers. When the
PS2CRn_PS/2_EN (n = 0-2) bit is set and the PS2CRn_
PS/2_T/R (n = 0-2) is cleared, the PS/2 hardware state
machine places data, received from the peripheral device,
into the receive register at the end of a successful receipt of
data. At the same time, the respective PS/2 clock line is
forced low by the PS/2 hardware to inhibit any further PS/2
transmission, and the PS2STSn_RDATA_RDY or
APS2STSn_RDATA_RDY (n = 0-2) bits inthe status regis-
ter or alternate status register are set indicating that data is
ready to be read by the software.
Thus, data received over PS/2 interface can be read from
the PS/2 receive register only when the PS2STSn_
RDATA_RDY or APS2STSn_RDATA_RDY (n=0-2) bits are
set. Reading this register while the PS2STSn_RDATA_
RDY or APS2STSn_RDATA_RDY (n=0-2) bits are cleared
always returns 0FFH.
The PS2STSn_RDATA_RDY or APS2STSn_RDATA_
RDY bits must be cleared by reading the status register in
order to allow the next PS/2 data reception or transmission.
©2006 Silicon Storage Technology, Inc.
183
S71320-01-000
10/06