SST79LF008 Datasheet, PDF (159/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
12.0 SERIAL PERIPHERAL INTERFACE (SPI)
Advance Information
12.1 SPI Features
• Master or slave operation
• 16 MHz bit frequency (max) master mode
• 8 MHz bit frequency (max) slave mode
• LSB first or MSB first data transfer
• Four programmable bit rates
• End of transmission interrupt (SPIF)
• Write collision flag protection (WCOL)
• Wake up from Idle (master and slave modes)
• Wake up from Power Down modes (slave mode
only)
12.2 SPI Description
The serial peripheral interface (SPI) allows full-duplex high-
speed synchronous data transfer between the
SST79LF008 and the peripheral devices.
Figure 12-1 shows the correspondence between master
and slave SPI devices. The SCK (GPIO5) pin is the clock
output for master mode and input for slave mode.
The SST79LF008 does not output SS#. If the
SST79LF008 is the master and there is only one slave
device, the slave’s SS# input can be tied low. If there is
more than one slave, N GPIOs can be used to select N
slaves. Another option is external generation of the SS#
inputs of multiple slave devices.
When SST79LF008 master mode is selected, the SPI
clock generator will start following a write to the
SST79LF008 device SPI data register. The written data is
then shifted out of the MOSI (GPIO3) pin into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be gener-
ated if the SPI Interrupt Enable bit (SPIE) is set.
When SST79LF008 slave mode is selected, an external
master generates SCK clock and drives the Slave Select
input pin SS# (GPIO6) low to select the SST79LF008 SPI
module as a slave. If the Slave Select input pin has not
been driven low, then the SST79LF008 SPI unit is not
active and the MOSI port can also be used as an input port
pin.
Clock Phase control bit (CPHA) and Clock Polarity
(CPOL) control the phase and polarity of the SPI clock. Fig-
ures 12-2 and 12-3 show the transfer formats with four pos-
sible combinations of these two bits.
To wake up the SST79LF008 from IDLE, whether in mas-
ter or slave mode, the following conditions must be met:
The SPIF bit is set to ‘1’ upon completion of the data trans-
fer, the SPIE is ‘1’, and EA (Enable Global Interrupt bit in
interrupt enable register) is ‘1’. These conditions generate
an interrupt that wakes the device from IDLE mode.
In slave mode only, the SST79LF008 wakes up from Power
Down when CPHA = 0 or CPHA = 1. When CPHA = 0, a
transition from high to low on SS# pin wakes up the device
from Power Down mode. When CPHA = 1, the clock edges
of SCK wakes up the device from Power Down mode.
MSB Master LSB
8-bit Shift Register
MISO
MOSI
MISO
MSB Slave LSB
8-bit Shift Register
MOSI
SPI Clock Generator
SCK
MISO = Master In Slave Out
MOSI = Master Out Slave In
FIGURE 12-1: SPI Master-Slave Interconnection
©2006 Silicon Storage Technology, Inc.
159
SCK
SS#
V_IL
1245 SPIMasterSlave.0
S71320-01-000
10/06