SST79LF008 Datasheet, PDF (229/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
Advance Information
TABLE 23-1: Configuration Registers Map¹ (Continued)
Index Access Type Reset Value² Configuration Register Name
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (ACPI ECI1)
30H
R/W
60H⁵, 61H
R/W
00H
00H, 68H
01H = Device is active.
00H = Device is inactive; the address of device is not decoded; LPC I/O read
and write cycles to the device are ignored.
ACPI ECI1 Data port LPC I/O address 0000:A[11:3]:0:A1:0
Command/Status port address = Data port address + 4
T23-1.1320
1. Register at indexes not listed in the map are reserved and must not be written to by software.
2. All configuration registers are returned to their reset values specified above after the following reset events: Power-On Reset, Exter-
nal reset, Watchdog timer reset, Brown-Out reset, aLPC Soft reset, LPC Soft reset, and Configuration Soft reset (see also Section
5.2).
3. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical
device. All accesses to device specific configuration registers with index above 30H (including the activate command) operate only
on the selected logical device.
4. The hardware automatically clears this bit after soft reset is completed; there is no need for software to clear this bit. This soft reset
only affects configuration registers.
5. Register at index 60H contains high byte of LPC I/O address - bits A[15:8], and register at index 61H contains low byte of LPC I/O
address- bits A[7:0].
©2006 Silicon Storage Technology, Inc.
229
S71320-01-000
10/06