SST79LF008 Datasheet, PDF (62/252 Pages) Silicon Storage Technology, Inc – Mobile Platform Controller plus 8 Mbit LPC Firmware Flash

Advance Information
4.8.5 aLPC I/O Write Operation
When the SST79LF008 device is switched into aLPC
mode it supports aLPC I/O Write and Read cycles in addi-
tion to the aLPC Memory Write and Read cycles previously
described. However, in aLPC mode all LPC logical I/O
devices are disabled (as all Configuration registers are
reset - see Section 23.2). Therefore the only useful
aLPC I/O operations are aLPC Write cycles utilized by the
aLPC Host to issue aLPC Snooper commands described
in Table 4-6. These cycles are similar to the standard LPC
I/O Write cycles except 4 clocks (instead of 1) are used to
transfer each field. The following exceptions with regards to
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
aLAD and aLFRAME# control are also applied to the
aLPC I/O cycles when the Snooper is in IDLE and READY
states:
• In IDLE and READY states the Snooper tri-states
the aLAD line and does not return RSYNC to the
Host
• In READY state the Snooper returns the status of
RDY4ALPC bit on aLFRAME# during SYNC
phase of the fourth write cycle of the
Enable_and_Poll sequence.
Examples of I/O Write cycles before and after entry to
SWITCHED state (aLPC mode) are shown in Figures 4-11
and 4-12, respectively.
TABLE 4-10: aLPC I/O Write Cycle Field Definitions
Clock
Cycle
Field
Name
Field
SST79LF008
Contents
aLAD Comments
0-3
START
0,0,0,0
IN¹
aLFRAME# must be active (low) for the part to respond. Only the last
four clocks of the start field (before aLFRAME# transitioning high)
should be recognized. The START field contents indicate aLPC Firm-
ware Memory Write cycle (value = 0000).
LSb MSb
Order of bit transfer for this field: LS Bit first
4-7
CYC_TYPE 0,1,0,0
IN¹
Cycle type field indicates aLPC I/O Write cycle (value - 0010)
LSb MSb
Order of bit transfer for this field: LS Bit first
8-23
ADDR
16-bit
address
IN¹
These 16 clock cycles make up the 16-bit I/O address A₁₅-A₀.
Order of bit transfer for this field: MS Nibble first, LS Bit first:
A12,A13,A14,A15, A8,A9,A10,A11, A4,A5,A6,A7, A0,A1,A2,A3
24-31
DATA
D0,D1,...D7
IN¹
These 8 clock cycles are used to transmit one Data byte.
LSb MSb
Order of bit transfer for this field: LS Bit first
32-35
TAR0
1,1,1,1
IN¹
In these 4 clock cycles, the aLPC host has driven the aLAD pin to ‘1’.
This is the first part of the bus turnaround.
36-39
TAR1
1,1,1,1
(float)
Float
The aLPC host floats the bus, and SST79LF008 takes control of the
bus after these 4 cycles, completing bus turnaround.
40-43
SYNC
0,0,0,0
OUT^2,3
During these 4 clock cycles, the SST79LF008 generates a ready-
sync (RSYNC) indicating that data is not ready, yet.
44-47
TAR0
1,1,1,1
OUT^2,3
In these 4 clock cycles, the aLPC host has driven the bus pin to ‘1’.
This is the first part of the bus turnaround.
48-51
TAR1
1,1,1,1
(float)
Float then SST79LF008 floats the bus, and the aLPC host resumes control of
IN¹
the bus after these 4 cycles, completing bus turnaround.
1. SST79LF008 reads field contents on the falling edge of the present clock cycle
2. Field contents are valid on the falling edge of the present clock cycle, and on the rising edge of the next clock cycle.
3. When the Snooper is in IDLE or READY state, aLAD is always floated in SST79LF008 (and SYNC = 1,1,1,1).
T4-10.0 1320
©2006 Silicon Storage Technology, Inc.
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S71320-01-000
10/06