SI5327 Datasheet, PDF(9/60 Page) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SI5327 Datasheet, PDF (9/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

◁

Si5327

Table 3. AC Specifications

(VDD = 1.8 Â± 5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

Input Voltage Swing

XARIN

XAVPP

RATE = M,

ac coupled

RATE = M,

ac coupled

Differential Reference Clock Input Pins (XA/XB)

kï

0.5

1.2

VPP

Input Voltage Swing

XA/XBVPP

RATE = M

0.5

2.4

VPP

CKINn Input Pins

Input Frequency

CKNF

0.002

Input Duty Cycle

(Minimum Pulse

Width)

CKNDC

Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

Input Capacitance

CKNCIN

Input Rise/Fall Time

CKNTRF

20â80%

See Figure 2

CKOUTn Output Pins

710

MHz

Output Frequency

(Output not config-

ured for CMOS or

Disabled)

CKOF

N1_HS ï³ 6

0.002

808

MHz

Maximum Output

Frequency in CMOS

Format

CKOF

212.5

MHz

Output Rise/Fall

(20â80 %) @

CKOTRF Output not configured for

230

350

CMOS or Disabled

622.08 MHz output

See Figure 2

Output Rise/Fall

(20â80%) @

212.5 MHz output

CKOTRF

CMOS Output

VDD = 1.71

CLOAD = 5 pF

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support

web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support

request regarding the lock time of your frequency plan.

Rev. 1.0

▷