SI5327 Datasheet, PDF (19/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

4. Functional Description
Si5327
Xtal or Refclock
CKIN1
CKIN2
÷ N31
÷ N32
Xtal/Refclock
Hitless Switching
Mux
DSPLL^®
÷ N2
÷ N1_HS
÷ N1_LS
÷ N2_LS
CKOUT1
CKOUT2
Loss of Signal/
Frequency Offset
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
I²C/SPI Port
Device Interrupt
Clock Select
Rate Select
Figure 7. Functional Block Diagram
The Si5327 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5327 accepts two input clocks
ranging from 2 kHz to 710 MHz and generates two
output clocks ranging from 2 kHz to 808 MHz. The
Si5327 can also use its crystal oscillator as a clock
source for frequency synthesis. The device provides
virtually any frequency translation combination across
this operating range. Independent dividers are available
for each input clock and output clock, so the Si5327 can
accept input clocks at different frequencies and it can
generate output clocks at different frequencies. The
Si5327 input clock frequency and clock multiplication
ratio are programmable through an I²C or SPI interface.
Silicon Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing.
The Si5327 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5327
PLL loop bandwidth is digitally programmable and
supports a range from 4 to 525 Hz. The DSPLLsim
software utility can be used to calculate valid loop
bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5327 supports hitless switching between the two
manually controlled synchronous input clocks in
compliance with GR-253-CORE that greatly minimizes
the propagation of phase transients to the clock outputs
during an input clock transition (maximum 200 ps phase
change). The Si5327 monitors both input clocks for
loss-of-signal (LOS) and provides a LOS alarm
(INT_LOS1 and LOS2) when it detects missing pulses
on either input clock. The device monitors the lock
status of the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. The Si5327
provides a digital hold capability that allows the device
to continue generation of a stable output clock when the
selected input reference is lost. During digital hold, the
DSPLL generates an output frequency based on a
historical average frequency that existed for a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
The Si5327 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
The device input to output skew is not specified. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
Rev. 1.0
19