SI5327 Datasheet, PDF (6/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5327
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Output Clocks (CKOUTn)^3,5
Test Condition
Min
Typ
Max
Unit
Common Mode
CKO_VCM
Differential Output
Swing
Single Ended Output
Swing
Differential Output
Voltage
Common Mode Out-
put Voltage
Differential Output
Voltage
CKO_VD
CKO_VSE
CKO_VD
CKO_VCM
CKO_VD
Common Mode
Output Voltage
Differential Output
Resistance
Output Voltage Low
CKO_VCM
CKO_RD
CKO_VOLLH
LVPECL 100  load V_DD –1.42
—
line-to-line
LVPECL 100  load
1.1
—
line-to-line
LVPECL 100  load line-
0.5
—
to-line
CML 100  load
line-to-line
350
425
CML 100  load
line-to-line
—
V_DD-0.36
LVDS
500
700
100  load line-to-line
Low Swing LVDS
350
425
100  load line-to-line
LVDS 100 load
line-to-line
1.125
1.2
CML, LVPECL, LVDS
—
200
CMOS
—
—
V_DD –1.25
1.9
0.93
500
—
900
500
1.275
—
0.4
V
V_PP
V_PP
mV_PP
V
mV_PP
mV_PP
V

V
Output Voltage High CKO_VOHLH
V_DD = 1.71 V
0.8 x V_DD
—
—
V
CMOS
Notes:
1. Current draw is independent of supply voltage.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal V_DD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6
Rev. 1.0