SI5327 Datasheet, PDF (13/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Table 4. Microprocessor Control (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
SPI Specifications
Symbol
Test Condition
Duty Cycle, SCLK
t_DC
SCLK = 10 MHz
Cycle Time, SCLK
t_c
Rise Time, SCLK
t_r
Fall Time, SCLK
t_f
20–80%
20–80%
Low Time, SCLK
t_lsc
High Time, SCLK
t_hsc
Delay Time, SCLK Fall
t_d1
to SDO Active
Delay Time, SCLK Fall
t_d2
to SDO Transition
Delay Time, SS Rise
t_d3
to SDO Tri-state
Setup Time, SS to
t_su1
SCLK Fall
Hold Time, SS to
t_h1
SCLK Rise
Setup Time, SDI to
t_su2
SCLK Rise
Hold Time, SDI to
t_h2
SCLK Rise
Delay Time between
t_cs
Slave Selects
20–20%
80–80%
Si5327
Min
Typ
Max
Unit
40
—
60
%
100
—
—
ns
—
—
25
ns
—
—
25
ns
30
—
—
ns
30
—
—
ns
—
—
25
ns
—
—
25
ns
—
—
25
ns
25
—
—
ns
20
—
—
ns
25
—
—
ns
20
—
—
ns
25
—
—
ns
Rev. 1.0
13