SI5327 Datasheet, PDF (1/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5327
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER
ATTENUATOR
Features
 Generates any frequency from 2 kHz  Dual clock inputs with manually
to 808 MHz from an input frequency controlled hitless switching
of 2 kHz to 710 MHz
 Free run and VCO freeze modes
 Ultra-low jitter clock outputs with jitter  Support for ITU G.709 and custom
generation as low as 0.5 ps rms
FEC ratios (255/238, 255/237,
(12 kHz–20 MHz)
255/236)
 Integrated loop filter with selectable  LOL and LOS alarm outputs
loop bandwidth (4 to 525 Hz)
 I²C or SPI programmable
 Meets OC-192 GR-253-CORE jitter _{ Single 1.8, 2.5, 3.3 V supply}
specifications
 Small size: 6 x 6 mm 36-lead QFN
 Pb-free, ROHS compliant
Applications
 Dual clock outputs with
 Synchronous Ethernet
programmable signal format
 Optical modules
(LVPECL, LVDS, CML, CMOS)
 Wireless repeaters/
 SONET/SDH OC-48/OC-192/STM-
wireless backhaul
16/STM-64 line cards
 Data converter clocking
 ITU G.709 and custom FEC line  xDSL
cards
 PDH clock synthesis
 GbE/10GbE, 1/2/4/8/10G Fibre
 Test and measurement
Channel line cards
 Broadcast video
Description
The Si5327 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
808 MHz. The two outputs are divided down separately from a common source.
The Si5327 can also use its crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency translation combination
across this operating range. The Si5327 input clock frequency and clock
multiplication ratio are programmable through an I²C or SPI interface. The Si5327
is based on Silicon Laboratories' 3rd-generation DSPLL^® technology, which
provides frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5327 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
Ordering Information:
See page 54.
Pin Assignments
36 35 34 33 32 31 30 29 28
RST 1
27 SDI
NC 2
26 A2_SS
INT_LOS1 3
25 A1
LOS2 4
VDD 5
XA 6
GND
Pad
24 A0
23 SDA_SDO
22 SCL
XB 7
21 CKSEL
GND 8
20 NC
NC 9
19 NC
10 11 12 13 14 15 16 17 18
Rev. 1.0 1/13
Copyright © 2013 by Silicon Laboratories
Si5327