SI5327 Datasheet, PDF (51/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5327
Pin # Pin Name I/O Signal Level
Description
18
LOL
O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked
1 = PLL unlocked
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
21
CKSEL
I
LVCMOS Input Clock Select.
This pin functions as the manual input clock selector.
0 = Select CKIN1
1 = Select CKIN2
CKSEL should not be left open and should be driven to either logic
high or logic low.
22
SCL
I
LVCMOS Serial Clock.
This pin functions as the serial clock input for both SPI and I²C
modes.
This pin has a weak pull-down.
23 SDA_SDO I/O LVCMOS Serial Data.
In I²C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial
data output.
25
A1
I
LVCMOS Serial Port Address.
24
A0
In I²C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I²C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
26
A2_SS
I
LVCMOS Serial Port Address/Slave Select.
In I²C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27
SDI
I
LVCMOS Serial Data In.
In I²C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Rev. 1.0
51