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SI5327 Datasheet, PDF (8/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5327
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
3-Level Input Pins4
Input Voltage Low
Input Voltage Mid
Symbol
VILL
VIMM
Input Voltage High
VIHH
Input Low Current
IILL
Input Mid Current
IIMM
Input High Current
IIHH
Test Condition
See Note 4
See Note 4
See Note 4
Min
Typ
Max
Unit
—
0.45 x
VDD
0.85 x
VDD
–20
–2
—
—
0.15 x VDD
V
—
0.55 x VDD
V
—
—
V
—
—
µA
—
+2
µA
—
20
µA
LVCMOS Output Pins
Output Voltage Low
VOL
IO = 2 mA
VDD = 1.71 V
—
—
0.4
V
Output Voltage Low
Output Voltage High
VOH
Output Voltage High
IO = 2 mA
VDD = 2.97 V
—
—
0.4
V
IO = –2 mA
VDD –0.4
—
—
V
VDD = 1.71 V
IO = –2 mA
VDD –0.4
—
—
V
VDD = 2.97 V
Notes:
1. Current draw is independent of supply voltage.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
8
Rev. 1.0