SI5327 Datasheet, PDF (24/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5327
Register 2.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
BWSEL_REG [3:0]
Type
R/W
R
R
R
R
Reset value = 0100 0010
Bit
Name
Function
7:4 BWSEL_REG BWSEL_REG.
[3:0]
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG
is written with a new value, an ICAL is required for the change to take effect.
3:0
Reserved
Register 3.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
VCO_FREEZE SQ_ICAL
Type
R
R/W
R/W
R
R
R
R
Reset value = 0000 0101
Bit
Name
Function
7:6
Reserved
5 VCO_FREEZE VCO_FREEZE.
Forces the part into VCO freeze. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force VCO freeze mode. Overrides all other settings and ignores the quality of all of
the input clocks.
4
SQ_ICAL SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 20.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Reserved
24
Rev. 1.0