SI5327 Datasheet, PDF (11/60 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5327
Table 3. AC Specifications (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
PLL Performance
(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 40 MHz)
Lock Time²
t_LOCKMP Start of ICAL to of LOL
—
Settle Time²
t_SETTLE
Start of ICAL to F_OUT
—
within 5 ppm of final value
Output Clock Phase
Change
Closed Loop Jitter
Peaking
Jitter Tolerance
t_{P_STEP}
J_PK
J_TOL
After clock switch
—
f3  128 kHz
—
Jitter Frequency Loop 5000/BW
Bandwidth
Phase Noise
fout = 622.08 MHz
100 Hz Offset
—
1 kHz Offset
—
Typ
1.9
5.5
200
0.05
—
–80
–110
Max
Unit
3
s
6.5
s
—
ps
0.1
dB
—
ns pk-pk
—
dBc/Hz
—
dBc/Hz
CKO_PN
10 kHz Offset
100 kHz Offset
—
–113
—
dBc/Hz
—
–117
—
dBc/Hz
1 MHz Offset
—
–125
—
dBc/Hz
Subharmonic Noise
SP_SUBH Phase Noise @ 100 kHz
—
–80
—
dBc
Offset
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
–65
—
dBc
(n  1, n x F3 < 100 MHz)
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan. Please visit the Silicon Labs Technical Support
web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support
request regarding the lock time of your frequency plan.
Rev. 1.0
11