SI5374 Datasheet, PDF (61/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
Table 11. Si5374 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal
Level
Description
E2
LOL_A
O LVCMOS DSPLLq Loss of Lock Indicator.
C5
LOL_B
These pins function as the active high PLL loss of lock indicator if
E8
LOL_C
the LOL_PIN register bit is set to 1.
H5
LOL_D
0 = PLL locked.
1 = PLL unlocked.
If LOL_PINn = 0, this pin will tri-state. Active polarity is controlled
by the LOL_POLn bit. The PLL lock status will always be
reflected in the LOL_INTn read only register bit (see application
note, "AN803: Lock and Settling Time Considerations for the
Si5324/27/69/74 Any-Frequency Jitter Attenuating Clock ICs).
D1
CS_CA_A I/O LVCMOS DSPLLq Input Clock Select/Active Clock Indicator.
A6
CS_CA_B
Input: In manual clock selection mode, this pin functions as the
F9
CS_CA_C
manual input clock selector if the CKSEL_PIN is set to 1.
J4
CS_CA_D
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates. If configured for input, must be
tied high or low.
Output: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active clock. If
alarms exist on both clocks, CK_ACTV will indicate the last active
clock that was used before entering the digital hold state. The
CK_ACTV_PIN register bit must be set to 1 to reflect the active
clock status to the CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
G5
SCL
I LVCMOS _I²_{C Serial Clock.}
This pin functions as the serial clock input.
This pin has a weak pull-down.
G6
SDA
I/O LVCMOS _I²_{C Serial Data.}
I²C pin functions as the bi-directional serial data port.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5374 Register Map.
Rev. 1.1
61