SI5374 Datasheet, PDF (2/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
Functional Block Diagram
CKIN1P_A
CKIN1N_A
CKIN2P_A
CKIN2N_A
Internal
Osc
CKIN3P_B
CKIN3N_B
CKIN4P_B
CKIN4N_B
Internal
Osc
CKIN5P_C
CKIN5N_C
CKIN6P_C
CKIN6N_C
Internal
Osc
CKIN7P_D
CKIN7N_D
CKIN8P_D
CKIN8N_D
Internal
Osc
Input Stage PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
Synthesis Stage
DSPLL^®
A
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
B
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
C
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
D
fOSC
÷ NC1_HS
÷ N2
RSTL_q
CS_CA_q
Status / Control
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Output Stage
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
High PSRR
Voltage Regulator
CKOUT1P_A
CKOUT1N_A
CKOUT2P_A
CKOUT2N_A
CKOUT3P_B
CKOUT3N_B
CKOUT4P_B
CKOUT4N_B
CKOUT5P_C
CKOUT5N_C
CKOUT6P_C
CKOUT6N_C
CKOUT7P_D
CKOUT7N_D
CKOUT8P_D
CKOUT8N_D
VDD_q
GND
2
Rev. 1.1