SI5374 Datasheet, PDF (16/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
The Si5374 is a highly integrated jitter-attenuating clock
multiplier that integrates four fully independent DSPLLs
and provides ultra-low jitter generation with less than
410 fs RMS. Configuration and control of the Si5374 is
mainly handled through the I²C interface. The device
accepts clock inputs ranging from 2 kHz to 710 MHz
and generates independent, synchronous clock outputs
ranging from 2 kHz to 808 MHz for each DSPLL.
Virtually any frequency translation (M/N) combination
across its operating range is supported. The Si5374
supports a digitally programmable loop bandwidth that
can range from 4 to 525 Hz requiring no external loop
filter components. An external single-ended or
differential reference clock or XO is required for the
device to enable ultra-low jitter generation and jitter
attenuation.
The device monitors each input clock for loss-of-signal
(LOS) and provides a LOS alarm when missing pulses
on any of the input clocks are detected. The device
monitors the lock status of each DSPLL and provides a
Loss-of-Lock (LOL) alarm when the DSPLL is unlocked.
The lock detect algorithm continuously monitors the
phase of the selected input clock in relation to the phase
of the feedback clock. See application note, "AN803:
Lock and Settling Time Considerations for the
Si5324/27/69/74 Any-Frequency Jitter Attenuating
Clock ICs."
The Si5374 provides a holdover capability that allows
the device to continue generation of a stable output
clock when the input reference is lost. The reference
oscillator can be internally routed into CKIN2_q, so free-
running clock generation is supported for each DSPLL
offering simultaneous synchronous and asynchronous
operation.
The output drivers are configurable to support common
signal formats, such as LVPECL, LVDS, CML, and
CMOS loads. If the CMOS signal format is selected,
each differential output buffer generates two in-phase
CMOS clocks at the same frequency. For system-level
debugging, a DSPLL bypass mode drives the clock
output directly from the selected input clock, bypassing
the internal DSPLL.
Silicon Laboratories offers a PC-based software utility,
Si537xDSPLLsim that can be used to determine valid
frequency plans and loop bandwidth settings to simplify
device setup. Si537xDSPLLsim provides the optimum
input, output, and feedback divider values for a given
input frequency and clock multiplication ratio that
minimizes phase noise. This utility can be downloaded
from http://www.silabs.com/timing. For further
assistance, refer to the Si53xx Any-Frequency Precision
Clocks Family Reference Manual.
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Rev. 1.1