SI5374 Datasheet, PDF (11/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
Table 5. Performance Specifications
V_DD = 1.8 V ±5% or 2.5 V ±10%, T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
PLL Performance¹
Lock Time² Si5374B-A-xL³
t_LOCKMP Start of ICAL to of LOL,
—
Si5374C-A-xL
FASTLOCK enabled
—
Settle Time² Si5374B-A-xL
t_SETTLE Start of ICAL to F_OUT within
—
5 ppm of final value
Si5374C-A-xL
—
Typ Max Unit
1
1.5
s
0.8
1.0
1.2
1.5
s
4.2
5.0
Output Clock Phase Change t_{P_STEP}
Closed Loop Jitter Peaking
Jitter Tolerance
J_PK
J_TOL
After clock switch
f3  128 kHz
Jitter Frequency Loop
Bandwidth
—
200
—
0.05
5000/BW —
—
ps
0.1
dB
—
ns
pk-pk
Phase Noise
fout = 622.08 MHz
CKO_PN
1 kHz Offset
10 kHz Offset
—
–106
— dBc/Hz
—
–114
— dBc/Hz
100 kHz Offset
1 MHz Offset
—
–116
— dBc/Hz
—
–132
— dBc/Hz
Spurious Noise
Jitter Generation
SP_SPUR
Max spur @ n x F3
—
–70
—
dBc
(n  1, n x F3 < 100 MHz)
J_GEN
f_IN = f_OUT = 622.08 MHz,
BW = 120 Hz
LVPECL output
12 kHz–20 MHz
—
350
410 fs rms
50 kHz–80 MHz
—
410
— fs rms
Notes:
1. fin = fout = 622.08 MHz; BW = 7 Hz; LVDS, OSC = .121.109 MHz.
2. Lock and settle time performance is dependent on the frequency plan and the OSC_P/OSC_N reference frequency
and LOCKT setting (see application note, "AN803: Lock and Settling Time Considerations for the Si5324/27/69/74
Any-Frequency Jitter Attenuating Clock ICs". Visit the Silicon Labs Technical Support web page at:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding
the lock time of your frequency plan.
3. LOCKT = 3.3 ms.
Rev. 1.1
11