SI5374 Datasheet, PDF (17/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
5. Si5374 Application Examples and
Suggestions
5.1. Schematic and PCB Layout
For a typical application schematic and PCB layout, see
the Si537x-EVB Evaluation Board User's Guide, which
can be downloaded from www.silabs.com/timing.
In order to preserve the ultra low jitter of the Si5374 in
applications where the four different DSPLL's are each
operating at different frequency, special care and
attention must be paid to the PCB layout. The following
is a list of rules that should be observed:
1. The four Vdd supplies should be isolated from one
another with four ferrite beads. They should be
separately bypassed with capacitors that are located
very close to the Si5374 device.
2. Use a solid and undisturbed ground plane for the
Si5374 and all of the clock input and output return
paths.
3. For applications that wish to logically connect the
four RESET signals, do not tie them together
underneath the BGA package. Instead connect them
outside of the BGA footprint.
4. As much as is possible, do not route clock input and
output signals underneath the BGA package. The
clock output signals should go directly outwards from
the BGA footprint.
5. Avoid placing the OSC_P and OSC_N signals on the
same layer as the clock outputs. Add grounded
guard traces surrounding the OSC_P and OSC_N
signals.
6. Where possible, place the CKOUT and CKIN signals
on separate PCB layers with a ground layer between
them. The use of ground guard traces between all
clock inputs and outputs is recommended.
For more information, see the Si537x-EVB Evaluation
Board User's Guide and Appendix I of the Si53xx
Reference Manual, Rev 0.5 or higher.
5.2. Thermal Considerations
The Si5374 dissipates a significant amount of heat and
it is important to take this into consideration when
designing the Si5374 operating environment. Among
other issues, high die temperatures can result in
increased jitter and decreased long term reliability. It is
therefore recommended that one or more of the
following occur:
1. Use a heat sink - A heat sink example is Aavid part
number 375324B00035G.
2. Use a Vdd voltage of 1.8 V.
3. Limit the ambient temperature to significantly less
that 85 °C.
4. Implement very good air flow.
5.3. SCL Leakage
When selecting pull up resistors for the two I²C signals,
note that there is an internal pull down resistor of 18 k
from the SCL pin to ground. This comment does not
apply to the SDA pin.
5.4. RSTL_x Pins
It is recommended that the four RSTL_x pins (RSTL_A,
RSTL_B, RSTL_C and RSTL_D) be logically connected
together such that all four DSPLLs are either in or out of
reset mode. When a DSPLL is in reset mode, its VCO
will not be locked to any signal and may drift across its
operating range. If a drifting VCO has a frequency
similar to that of an operating VCO, there could be
some crosstalk between the two VCOs. To avoid this
from occurring during device initialization, DSPLLsim
loads each DSPLL with default Free Run frequency
plans with VCO values apart from one another. If the
four RSTL_x pins are directly connected to one another,
the connections should not be made directly underneath
the BGA package. Instead, the connections should be
made outside the package footprint.
5.5. Reference Oscillator Selection
Care should be taken during the selection of the
external oscillator that is connected to the OSC_P and
OSC_N pins. There is no jitter attenuation from the OSC
reference inputs to the output; so, to achieve low output
jitter, a low-jitter reference OSC must be used. Also, the
output drift during holdover will be the same as the drift
of the OSC reference. For example, a Stratum 3
application will require an OSC reference source that
has Stratum 3 stability (though Stratum 3 accuracy is
not required).
The OSC frequency can be any value from 109 to
125.5 MHz. See the RATE_REG (reg 2) description.
Alternately, for applications with less demanding jitter
requirements, the OSC frequency can be in the range
from 37 to 41 MHz. For applications that use Free Run
mode, the freedom to use any OSC frequency within
these bands can be used to select an OSC frequency
that has an integer relationship to the desired output
frequency, which will make it easier to find a high-
performance frequency plan.
If Free Run is not being used, an OSC frequency that is
not integer-related to the output frequency is preferred.
A recommended choice for an external oscillator is the
Silicon Labs 530EB121M109DG, which is a 2.5 V,
LVPECL device with a temperature stability of 20 ppm.
It was used to take the typical phase noise plot on
page 14. For more details and a more complete
discussion of these topics, see the Si53xx Reference
Manual.
The very low loop BW of the Si5374 means that it can
be susceptible to OSC_P/OSC_N reference sources
Rev. 1.1
17