SI5374 Datasheet, PDF (1/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
4-PLL ANY-FREQUENCY PRECISION CLOCK
MULTIPLIER/JITTER ATTENUATOR
Features
 Highly-integrated, 4 PLL clock
 Supports all ITU G.709 and any
multiplier/jitter attenuator
custom FEC ratios (239/237,
 Four independent DSPLLs support
any-frequency synthesis and jitter
255/238, 255/237, 255/236,
253/226)
attenuation
 Integrated loop filter with
 8 inputs/8 outputs
programmable bandwidth
 Each DSPLL can generate any ^{ Simultaneous free-run and}
frequency from 2 kHz to 808 MHz
synchronous operation
from a 2 kHz to 710 MHz input
 Automatic/manual hitless input clock
 Ultra-low jitter clock outputs:
switching
350 fs rms (12 kHz–20 MHz) and  Selectable output clock signal
410 fs rms (50 kHz–80 MHz) typical format (LVPECL, LVDS, CML,
 Meets ITU-T G.8251 and Telcordia
CMOS)
GR-253-CORE OC-192 jitter
 LOL and interrupt alarm outputs
specifications
 I²C programmable
 Single 1.8 V ±5% or 2.5 V ±10%
operation with high PSRR on-chip
voltage regulator
 10x10 mm PBGA
Applications
 High-density, any-port, any-protocol,  1/2/4/8/10G Fibre Channel
any-frequency line cards
 GbE/10 GbE Synchronous Ethernet
 ITU-T G.709 OTN custom FEC
 Carrier Ethernet, multi-service
 10/40/100G
switches and routers
 OC-48/192, STM-16/64
 MSPP, ROADM, P-OTS,
muxponders
Description
The Si5374 is a highly-integrated, 4-PLL, jitter-attenuating precision clock
multiplier for applications requiring sub-1 ps jitter performance. Each of the
DSPLL^® clock multiplier engines accepts two input clocks ranging from 2 kHz to
710 MHz and generates two independent synchronous output clocks ranging
from 2 kHz to 808 MHz. The device provides virtually any frequency translation
combination across this operating range. For asynchronous, free-running clock
generation applications, the Si5374’s reference oscillator can be used as a clock
source for any of the four DSPLLs. The Si5374 input clock frequency and clock
multiplication ratio are programmable through an I²C interface. The Si5374 is
based on Silicon Laboratories’ third-generation DSPLL^® technology, which
provides any-frequency synthesis and jitter attenuation in a highly-integrated
PLL solution that eliminates the need for external VCXO and loop filter
components. Each DSPLL loop bandwidth is digitally-programmable, providing
jitter performance optimization at the application level. The device operates from
a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR.
The Si5374 is ideal for providing clock multiplication and jitter attenuation in
high-port-count optical line cards requiring independent timing domains.
Ordering Information:
See page 63.
Rev. 1.1 1/14
Copyright © 2014 by Silicon Laboratories
Si5374