SI5374 Datasheet, PDF (22/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5374
7. Register Descriptions
Register 0.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FREE_RUN CKOUT_ALWAYS_ON
BYPASS_REG
Type
R
R/W
R/W
R
R
R
R/W
R
Reset value = 0001 0100
Bit
Name
Function
7
Reserved
Reserved.
6
FREE_RUN
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the DSPLL to lock to
its XA-XB reference to support free-running clock generation.
0: Disable
1: Enable
5 CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_I-
CAL is on and ICAL is not complete or successful. See Table 9 on page 56.
0: Squelch output until device is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the device is calibrated.
2. Must be set to 1 to control output to output skew.
4:2
Reserved
Reserved.
1
BYPASS_REG
Bypass Register.
This bit enables or disables PLL bypass mode. Use only when the device is in
digital hold or before the first ICAL. Bypass mode does not support CMOS
clock outputs.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypass-
ing PLL.
0
Reserved
Reserved.
22
Rev. 1.1