SI5374 Datasheet, PDF(52/69 Page) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5374 Datasheet, PDF (52/69 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5374

Bit

Name RST_REG ICAL

Type

R/W

Reset value = 0000 0000

Bit

Name

Function

RST_REG Internal Reset (Same as Pin Reset).

Note: The I2C port may not be accessed until 10 ms after RST_REG is asserted.

0: Normal operation.

1: Reset all internal logic. Outputs disabled or tristated during reset.

ICAL

Start Internal Calibration Sequence.

For proper operation, the device must go through an internal calibration sequence.

ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-

tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)

must be present to begin ICAL.

Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take

effect.

0: Normal operation.

1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-

bration, LOL will go low.

5:0

Reserved

Bit

Name

FASTLOCK

Type

R/W

Reset value = 0000 0000

Bit

Name

Function

7:1

Reserved

Do not modify.

FASTLOCK This bit must be set to 1 to enable FASTLOCK.

This improves initial lock time by dynamically changing the loop bandwidth during

PLL lock acquisition.

Rev. 1.1

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