SI5345 Datasheet, PDF (6/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 3. Input Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Unit
Standard Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Input Frequency Range
Voltage Swing¹
Slew Rate^{2, 3}
f_{IN_DIFF}
V_IN
SR
Differential
Single-ended/LVCMOS
Differential AC Coupled
f_in < 250 MHz
Differential AC Coupled
250 MHz < f_in < 750 MHz
Single-Ended AC Coupled
f_in < 250 MHz
0.008
0.008
100
225
100
400
— 750
MHz
— 250
MHz
— 1800 mVpp_se
— 1800 mVpp_se
— 3600 mVpp_se
—
—
V/μs
Duty Cycle
DC
40
— 60
%
Capacitance
C_IN
—
2
—
pF
Pulsed CMOS - DC Coupled (IN0, IN1, IN2, IN3)
Input Frequency
Input Voltage⁴
f_{IN_PULSED_CMOS4}
V_IL
V_IH
Slew Rate^{2, 3}
SR
0.008 — 250
–0.2 — 0.33
0.49
—
—
400
—
—
MHz
V
V
V/μs
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
k
REFCLK (applied to XA/XB)
Notes:
1. Voltage swing is specified as single-ended mVpp.
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR
4. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they
have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse.
Since the input thresholds (V_IL, V_IH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input
attenuator circuit for dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/
Support%20Documents/TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the
Standard Differential or Single-Ended ac-coupled input mode.
6
Rev. 1.0