SI5345 Datasheet, PDF (41/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
5.8.9. Output Enable/Disable
The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high
all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be
individually disabled through register control.
5.8.10. Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance.
5.8.11. Synchronous Output Disable Feature
The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will
wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from
occurring when disabling an output. When this feature is turned off, the output clock will disable immediately
without waiting for the period to complete.
5.8.12. Output Skew Control (t₀ – t₄)
The Si5345 uses independent MultiSynth dividers (N₀ - N₄) to generate up to 5 unique frequencies to its 10 outputs
through a crosspoint switch. By default all clocks are phase aligned. A delay path (t₀ - t₄) associated with each of
these dividers is available for applications that need a specific output skew configuration. This is useful for PCB
trace length mismatch compensation. The resolution of the phase adjustment is approximately 0.28 ps per step
definable in a range of ±9.14 ns. Phase adjustments are register configurable. An example of generating two
frequencies with unique configurable path delays is shown in Figure 25.
Figure 25. Example of Independently Configurable Path Delays
All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RST pin.
Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or
after power-on reset, or after a hardware reset using the RST pin.
Rev. 1.0
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