SI5345 Datasheet, PDF (10/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 5. Differential Clock Output Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Common Mode Volt-
age^1,2
(100 Ω load line-to-line)
Normal Mode or Low-Power Mode
V_CM
V_DDO = 3.3 V
LVDS
1.10 1.25 1.35
V
LVPECL
1.90 2.05 2.15
V
V_DDO = 2.5 V
LVPECL
1.15 1.25 1.35
V
LVDS
Rise and Fall Times
(20% to 80%)
V_DDO = 1.8 V
Sub-LVDS 0.87 0.93 1.0
V
t_R/t_F
Normal Mode
— 170 240
ps
Low-Power Mode
— 300 430
Differential Output
Impedance³
Z_O
Normal Mode
Low-Power Mode
— 100 —

— 650 —

Note:
1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register
settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or
low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Also note that the
output voltage swing specifications are given in peak-to-peak single-ended swing.
2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family
Reference Manual for details.
3. Driver output impedance depends on selected output mode (Normal, Low-Power).
4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO
(1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured.
5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor
at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure
Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring
crosstalk.
10
Rev. 1.0