SI5345 Datasheet, PDF (12/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 6. LVCMOS Clock Output Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Output Frequency
Duty Cycle
f_OUT
DC
Output-to-Output Skew
T_SK
Output Voltage High^{1, 2, 3} V_OH
0.0001 —
f_OUT <100 MHz
100 MHz < f_OUT < 250 MHz
47 —
44 —
—
—
OUTx_CMOS_DRV = 1
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
OUTx_CMOS_DRV = 1
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
V_DDO = 3.3 V
I_OH = –10 mA V_DDO x —
I_OH = –12 mA
0.85
—
I_OH = –17 mA
—
V_DDO = 2.5 V
I_OH = –6 mA V_DDO x —
I_OH = –8 mA
0.85
—
I_OH = –11 mA
—
V_DDO = 1.8 V
I_OH = –4 mA V_DDO x —
I_OH = –5 mA
0.85
—
250 MHz
53
%
55
100 ps
—
V
—
—
—
V
—
—
—
V
—
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5345/44/42 Family Reference Manual for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
12
Rev. 1.0