SI5345 Datasheet, PDF (34/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
5.6.6. Synchronizing to Gapped Input Clocks
The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock.
The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of
its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low
loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped
clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with
one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in
Figure 15. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”.
Figure 15. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out
of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching
between gapped clocks may violate the hitless switching specification in Table 8 when the switch occurs during a
gap in either input clock.
5.7. Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF)
as shown in Figure 16. The reference at the XA/XB pins is also monitored for LOS since it provides a critical
reference clock for the DSPLL. There is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL
loses synchronization.
Figure 16. Si5345/44/42 Fault Monitors
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