SI5345 Datasheet, PDF(40/62 Page) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

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SI5345 Datasheet, PDF (40/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

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Si5345/44/42

5.8.5. Differential Output Swing Modes

There are two selectable differential output swing modes: Normal and Low-Power. Each output can support a

unique mode. Please see the Si5345/44/42 Reference Manual for information on setting the differential output

driver to non-standard amplitudes.

ï®ï Differential Normal Swing Mode: When an output driver is configured in normal swing mode, its output

swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of

100 mV. The output impedance in the Normal Swing Mode is 100ïï differentialï®ï Any of the terminations

shown in Figure 23 is supported in this mode.

ï®ï Differential Low Power Mode: When an output driver is configured in low power mode, its output swing is

configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV.

The output driver is in high impedance mode and supports standard 50 ïï PCB traces. Any of the

terminations shown in Figure 23 is supported in this mode.

5.8.6. LVCMOS Output Impedance Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source

termination resistor is recommended to help match the selected output impedance to the trace impedance, where

Rs = Transmission line impedance â ZO. There are three programmable output impedance selections (CMOS1,

CMOS2, CMOS3) for each VDDO options as shown in Table 16.

VDDO

3.3 V

2.5 V

1.8 V

Table 16. Typical Output Impedance (ZS)

CMOS_DRIVE_Selection

CMOS1

38 ï

43 ï

CMOS2

30 ï

35 ï

46 ï

CMOS3

22 ï

24 ï

31 ï

5.8.7. LVCMOS Output Signal Swing

The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output

driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output

driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage.

5.8.8. LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By

default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin.

The polarity of these clocks is configurable enabling complementary clock generation and/or inverted polarity with

respect to other output drivers.

Rev. 1.0

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