SI5345 Datasheet, PDF (18/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 10. SPI Timing Specifications (4-Wire)
(V_DD = 1.8 V ±5%, V_DDA = 3.3V ±5%, T_A = –40 to 85 °C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CS Rise to SDO Tri-State
Setup Time, CS to SCLK
Hold Time, SCLK Fall to CS
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
Symbol
Min
Typ
Max
Unit
f_SPI
T_DC
T_C
T_D1
T_D2
T_D3
T_SU1
T_H1
T_SU2
T_H2
T_CS
—
—
20
MHz
40
—
60
%
50
—
—
ns
—
12.5
18
ns
—
10
15
ns
—
10
15
ns
5
—
—
ns
5
—
—
ns
5
—
—
ns
5
—
—
ns
2
—
—
T_C
Figure 3. 4-Wire SPI Serial Interface Timing
18
Rev. 1.0