SI5345 Datasheet, PDF (1/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
1 0 - C H A N N E L, A N Y- F R E Q U E N C Y, A N Y- O U T P U T J I T T E R
A T T E N U A T O R/ C L O C K M U L T I P L I E R
Features
 Generates any combination of output 
frequencies from any input frequency 
 Input frequency range:
Differential: 8 kHz to 750 MHz

LVCMOS: 8 kHz to 250 MHz
 Output frequency range:

Differential: up to 712.5 MHz

LVCMOS: up to 250 MHz
 Ultra-low jitter:
<100 fs typ (12 kHz–20 MHz)

 Programmable jitter attenuation
bandwidth from 0.1 Hz to 4 kHz



Meets G.8262 EEC Opt 1, 2 (SyncE)
Highly configurable outputs compatible
with LVDS, LVPECL, LVCMOS, CML,


and HCSL with programmable signal
amplitude

 Status monitoring (LOS, OOF, LOL)
 Hitless input clock switching: automatic ^
or manual

 Locks to gapped clock inputs

 Automatic free-run and holdover

modes

Optional zero delay mode
Fastlock feature for low nominal
bandwidths
Glitchless on the fly output frequency
changes
DCO mode: as low as 0.001 ppb steps.
Core voltage
V_DD: 1.8 V ±5%
V_DDA: 3.3 V ±5%
Independent output clock supply pins:
3.3 V, 2.5 V, or 1.8 V
Output-output skew: 20 ps typ
Serial interface: I²C or SPI
In-circuit programmable with
non-volatile OTP memory
ClockBuilder Pro^TM software simplifies
device configuration
Si5345: 4 input, 10 output, 64 QFN
Si5344: 4 input, 4 output, 44 QFN
Si5342: 4 input, 2 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Ordering Information:
See section 8
Functional Block Diagram
Device Selector Guide
Grade
Si534fA
Si534fB
Si534fC
Si534fD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Modes
Integer+Fractional
Integer+Fractional
Integer
Integer
Applications
 OTN Muxponders and Transponders  Carrier Ethernet switches
 10/40/100G networking line cards  SONET/SDH Line Cards
 GbE/10GbE/100GbE Synchronous  Broadcast video
Ethernet (ITU-T G.8262)
 Test and measurement
 ITU-T G.8262 (SyncE) Compliant
Description
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-
volatile memory (NVM) so they always power up with a known frequency configuration.
They support free-run, synchronous, and holdover modes of operation, and offer both
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Further, the
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with Silicon
Labs’ ClockBuilder Pro software. Factory preprogrammed devices are also available.
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5345/44/42