SI5345 Datasheet, PDF (48/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions
Pin Number
Pin Name
Pin Type¹
Si5345 Si5344 Si5342
Function
Inputs
XA
XB
8
5
5
9
6
6
I
Crystal Input
I
Input pins for external crystal (XTAL). Alternatively these
pins can be driven with an external reference clock (REF-
CLK). An internal register bit selects XTAL or REFCLK
mode. Default is XTAL mode.
X1
7
4
4
X2
10
7
7
I
XTAL Shield
I
Connect these pins directly to the XTAL ground pins. X1,
X2 and the XTAL ground pins should be separated from
the PCB ground plane. Refer to the Si5345/44/42 Family
Reference Manual for layout guidelines. These pins
should be left disconnected when connecting XA/XB pins
to an external reference clock (REFCLK).
IN0
63
43
43
I
Clock Inputs
IN0
64
44
44
I
These pins accept an input clock for synchronizing the
device. They support both differential and single-ended
IN1
1
1
1
I
clock signals. Refer to "5.6.5. Input Configuration and Ter-
minations" on page 32 for input termination options.
IN1
2
2
2
I
These pins are high-impedance and must be terminated
IN2
14
10
10
I
externally. The negative side of the differential input must
be grounded through a capacitor when accepting a sin-
IN2
15
11
11
I
gle-ended clock.
IN3/FB_IN 61
41
41
IN3/FB_IN 62
42
42
I
Clock Input 3/External Feedback Input
I
By default these pins are used as the fourth clock input
(IN3/IN3). They can also be used as the external feed-
back input (FB_IN/FB_IN) for the optional zero delay
mode. See section "5.8.13. Zero Delay Mode" on page 42
for details on the optional zero delay mode.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
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Rev. 1.0