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SI5345 Datasheet, PDF (46/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER | |||
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Si5345/44/42
Table 18. High-Level Register Map (Continued)
16-Bit Address
8-bit Page
Address
8-bit Register
Address Range
03
01
02â37
0C
17
22
2D
38
39â58
59â62
FE
04
87
05
0E - 14
15â1F
2A
2B
2Câ35
36
38â39
3F
06â08
00âFF
09
01
1C
43
49
10âFF
00âFF
Content
Set Page Address
MultiSynth Divider (N0âN4) Settings
MultiSynth Divider (N0) Update Bit
MultiSynth Divider (N1) Update Bit
MultiSynth Divider (N2) Update Bit
MultiSynth Divider (N3) Update Bit
MultiSynth Divider (N4) Update Bit
FINC/FDEC Settings N0 - N4
Output Delay (ït) Settings
Device Ready Status
Zero Delay Mode Set Up
Fast Lock Loop Bandwidth
Feedback Divider (M) Settings
Input Select Control
Fast Lock Control
Holdover Settings
Input Clock Switching Mode Select
Input Priority Settings
Holdover History Valid Data
Reserved
Set Page Address
Zero Delay Mode Settings
Control I/O Voltage Select
Input Settings
Reserved
46
Rev. 1.0
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