SI5345 Datasheet, PDF (49/62 Pages) Silicon Laboratories – 10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Name
Outputs
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
Pin Number
Pin Type¹
Si5345 Si5344 Si5342
Function
24
20
20
23
19
19
28
25
25
27
24
24
31
31
—
30
30
—
35
36
—
34
35
—
38
—
—
37
—
—
42
—
—
41
—
—
45
—
—
44
—
—
51
—
—
50
—
—
54
—
—
53
—
—
59
—
—
58
—
—
O
Output Clocks
O
These output clocks support a programmable signal
swing and common mode voltage. Desired output signal
O
format is configurable using register control. Termination
recommendations are provided in “5.8.3. Differential Out-
O
put Terminations” and section “5.8.4. LVCMOS Output
O
Terminations” . Unused outputs should be left uncon-
nected.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
Rev. 1.0
49