S1003 Datasheet, PDF (31/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
V_IH^*1
Input voltage
V_IL^*2
V_DD^*3
Output voltage
1 μs
t_PHL
1 μs
R^*1
t_PLH
V_DD
V_DD^*3 × 90%
+
VDD
MR
OUT
V _{VSS CD}
*2
C_OUT
100 kΩ
+ ^VDD1*1
V
V_DD^*3 × 10%
*1. V_IH = 10 V
*2. V_IL = 0.95 V
*3. CMOS output product: V_DD
Nch open-drain product: V_DD1
Figure 34 Test Condition of Response Time
*1. R and V_DD1 are unnecessary for CMOS output
product.
*2. Set to V_DD or GND (MR pin non-active).
Figure 35 Test Circuit of Response Time
Caution
1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. When the CD pin is open, a double pulse may appear at release.
To avoid the double pulse, attach a 100 pF or more capacitor to the CD pin.
Response time when detecting (t_PHL) is not affected by CD pin capacitance. Besides, response
time when releasing (t_PLH) can set the delay time by attaching the CD pin.
Refer to "11. Delay time (t_D) vs. CD pin capacitance (C_D) (Without output pin capacitance)" for
details.
11. Delay time (t_D) vs. CD pin capacitance (C_D) (Without output pin capacitance)
S-1003NA12
10000
Ta = +25°C
S-1003NA24
10000
1000
1000
100
100
10
10
1
1
0.1
0.1
0.01
0.01 0.1
1
10
CD [nF]
100 1000
0.01
0.01 0.1
1
10
CD [nF]
Ta = +25°C
100 1000
S-1003NA50
10000
1000
100
10
1
0.1
0.01
0.01 0.1
Ta = +25°C
1
10
CD [nF]
100 1000
Seiko Instruments Inc.
31