S1003 Datasheet, PDF (17/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
2. 2 S-1003 Series xB type (MR pin logic active "H")
(1) MR pin = "H"
When the VDD pin voltage is the release voltage (+V_DET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "H" (V_MRH) or more is applied to the
MR pin.
(2) MR pin = "L"
If a voltage of the MR pin input voltage "L" (V_MRL) or less is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (t_D), the OUT pin changes to the release status from the detection status.
Input from VDD pin
(1)
(2)
V_DD (≥ +V_DET)
Input from MR pin
MR pin input voltage "H" (V_MRH)
MR pin input voltage "L" (V_MRL)
V_DD
Output from OUT pin
V_SS
t_D
Figure 20 Timing Chart of MR Pin Logic Active "H"
Remark Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or
"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).
VDD
*1
MR
R_MR
*1
VSS
*1. Parasitic diode
Figure 21
Seiko Instruments Inc.
17