S1003 Datasheet, PDF (16/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
2. Manual reset function
The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (V_MR).
When not using the manual reset function, set V_MR = V_DD in the S-1003 Series xA type, and V_MR = V_SS in the
S-1003 Series xB type.
Caution Perform thorough evaluation in the actual application when using the MR pin in open. Due to the
parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply
fluctuates.
2. 1 S-1003 Series xA type (MR pin logic active "L")
(1) MR pin = "L"
When the VDD pin voltage is the release voltage (+V_DET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "L" (V_MRL) or less is applied to the
MR pin.
(2) MR pin = "H"
If a voltage of the MR pin input voltage "H" (V_MRH) or more is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (t_D), the OUT pin changes to the release status from the detection status.
Input from VDD pin
(1)
(2)
V_DD (≥ +V_DET)
Input from MR pin
MR pin input voltage "H" (V_MRH)
MR pin input voltage "L" (V_MRL)
V_DD
Output from OUT pin
V_SS
t_D
Figure 18 Timing Chart of MR Pin Logic Active "L"
Remark Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in
the floating status depending on the VDD pin voltage (Refer to Figure 19).
R_MR
VDD
*1
MR
*1
VSS
*1. Parasitic diode
Figure 19
16
Seiko Instruments Inc.