S1003 Datasheet, PDF (20/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series
Rev.1.0_00
3. Delay circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (V_DD)
exceeds the release voltage (+V_DET) when V_DD is turned on. The output signal is not delayed when V_DD decreases
to the detection voltage (−V_DET) or less (refer to "Figure 17 Operation 2").
The delay time (t_D) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached delay capacitor (C_D), or the delay time (t_D0) when the CD pin is open, and calculated from the following
equation. When the C_D value is sufficiently large, the t_D0 value can be disregarded.
t_D [ms] = Delay coefficient × C_D [nF] + t_D0 [ms]
Operation
Temperature
Ta = +85°C
Ta = +25°C
Ta = −40°C
Table 12 Delay Coefficient
Delay Coefficient
Min.
Typ.
1.60
1.89
1.78
2.05
2.01
2.31
Max.
2.13
2.30
2.71
Operation Temperature
Ta = −40°C to +85°C
Table 13 Delay Time
Min.
0.021 ms
Delay Time (t_D0)
Typ.
0.044 ms
Max.
0.147 ms
Caution 1.
When the CD pin is open, a double pulse shown in Figure 25 may appear at release.
To avoid the double pulse, attach a 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
V_OUT
Figure 25
Time
2. Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
3. There is no limit for the capacitance of C_D as long as the leakage current of the capacitor can
be ignored against the built-in constant current value. Leakage current causes deviation in
delay time. When the leakage current is larger than the built-in constant current, no release
takes place.
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Seiko Instruments Inc.