S1003 Datasheet, PDF (19/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
2. 4 When connecting resistance (R_A) between power supply voltage (V_DD) and VDD pin
When the MR pin voltage (V_MR) is an intermediate voltage (especially V_MRL < V_MR < V_MRH), the current consumption
increases by 25 μA max. A voltage drop occurs since this current flows through R_A. If the VDD pin voltage (V_IN)
becomes the detection voltage (−V_DET) or less for that reason, the OUT pin changes to the detection status, and the
detection status or the release status are not controlled by V_MR. The OUT pin may not be able to change to the
release status unless V_DD is raised (Refer to Figure 24).
(1) When MR pin logic is active "L"
In case of V_IN > V_MR, a current also flows through the MR pin input resistance (R_MR). For example, when V_IN =
10 V, V_MR = 1 V, R_MR = 0.5 MΩ (min.), a current of 18 μA flows from the VDD pin to the MR pin. Therefore, set
R_A so as to satisfy the following equation.
R_A ≤ (V_DD − (−V_DET)) / (25 μA + MR pin current)
(2) When MR pin logic is active "H"
Set R_A so as to satisfy the following equation.
R_A ≤ (V_DD − (−V_DET)) / 25 μA
V_DD
GND
R_A
V_IN
VDD
MR
VSS
V_MR
OUT
CD
(Nch open-drain output product)
Figure 24
Seiko Instruments Inc.
19