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S1003 Datasheet, PDF (15/42 Pages) Seiko Instruments Inc – MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_00
S-1003 Series
„ Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 16 is OFF, the comparator
input voltage is
(RB + RC ) • VDD
RA + RB + RC
.
(2) Although VDD decreases to +VDET or less, VDD is output when VDD is higher than the detection voltage (−VDET).
When VDD decreases to −VDET or less (point A in Figure 17), the Nch transistor is ON and the Pch transistor
is OFF so that VSS ("L") is output. At this time, the Nch transistor N1 in Figure 16 is turned on, and the input
voltage to the comparator is
RB • VDD
RA + RB
.
(3) The output is indefinite by decreasing VDD to the IC's minimum operation voltage or less. If the output is
pulled up, it will be VDD.
(4) VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds −VDET and
VDD is less than +VDET, the output is VSS.
(5) When increasing VDD to +VDET or more (point B in Figure 17), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
VSS
RA
+
*1
−
RB
VREF
RC
N1
*1
Pch
Delay
circuit
Nch
MR
circuit
*1
*1
*1
OUT
*1
MR
CD
CD
*1. Parasitic diode
Figure 16 Operation 1
(1) (2) (3) (4)
B
Hysteresis width
A
(VHYS)
(5)
VDD
Release voltage (+VDET)
Detection voltage (−VDET)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
Remark
tD
When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 17 Operation 2
Seiko Instruments Inc.
15
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