M166 Datasheet, PDF (72/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Instruction Description
EXTSRBegin EXTended Segment and Register SequenceEXTSR
Syntax
Operation
Description
Note
EXTSR op1, op2
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Segment = (op1) AND SFR_range = Extended
DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE)
Next Instruction
(count) ← (count) - 1
END WHILE
(count) = 0
Data_Page = (DPPx) AND SFR_range = Standard
Enable interrupts and traps
Overrides the standard DPP addressing scheme of the long and indirect
addressing modes and causes all SFR or SFR bit accesses via the ’reg’,
’bitoff’ or ’bitaddr’ addressing modes being made to the Extended SFR
space for a specified number of instructions. During their execution, both
standard and PEC interrupts and class A hardware traps are locked. The
EXTSR instruction becomes immediately active such that no additional
NOPs are required.
For any long (’mem’) or indirect ([...]) address in an EXTSR instruction
sequence, the value of op1 determines the 8-bit segment (address bits
A23-A16) valid for the corresponding data access. The long or indirect
address itself represents the 16-bit segment offset (address bits A15-A0).
The value of op2 defines the length of the effected instruction sequence.
The EXTSR instruction must be used carefully (see introductory note).
The EXTSR instruction is not available in the SAB 8XC166(W) devices.
Condition Flags
E
Z
V
C
N
-
-
-
-
-
Addressing Modes
E Not affected.
Z Not affected.
V Not affected.
C Not affected.
N Not affected.
Mnemonic
EXTSR Rwm, #irang2
EXTSR #seg, #irang2
Format
DC :10##-m
D7 :10##-0 ss 00
Bytes
2
4
Semiconductor Group
72
Version 1.2, 12.97